IBM squashes 30 bn transistors into fingernail-sized chip

IBM Research scientist Nicolas Loubet holds a wafer of chips with 5nm silicon nanosheet transistors manufactured using an industry-first process that can deliver 40 percent performance enhancement at fixed power or 75 percent power savings at matched per

IBM Research scientist Nicolas Loubet holds a wafer of chips with 5nm silicon nanosheet transistors manufactured using an industry-first process that can deliver 40 percent performance enhancement at fixed power or 75 percent power savings at matched per

In a project alongside Globalfoundries (Gloflo) and Samsung, the company used silicon nanosheets to build something even smaller than the current, seemingly unassailable (though of course it was always going to be eventually) 7nm chip, the smallest to use the fin field or FinFET design.

In an overview of the Nanosheet chip fabrication technology, the IBM blog explained that it has been using "stacks of silicon nanosheets as the device structure of the transistor, instead of the standard FinFET architecture, which is the blueprint for the semiconductor industry up through 7nm node technology".

While even most of the advanced chips developed today employ the FinFET process, which includes a circuitry that's 10-nanometer in width. Compared to leading edge 10nm chips the nanosheet-based 5nm technology "can deliver 40 per cent performance enhancement at fixed power, or 75 per cent power savings at matched performance", claims IBM. The nanosheet transistor sends electrons through four gates, whereas the current-generation FinFET transistor design that sends electrons through three gates.

Developed in collaboration with Research Alliance partners, GlobalFoundaries and Samsung, the chip will pack 30 billion 5nm switches onto a chip the size of a fingernail.

"This announcement is the latest example of the world-class research that continues to emerge from our groundbreaking public-private partnership in NY", said Gary Patton, CTO and Head of Worldwide R&D at Globalfoundries. It is believed that the said architecture will introduce some huge improvements in future demands of artificial intelligence (AI) systems, virtual reality and mobile devices.

This technology makes it possible for IBM to continually adjust individual circuits to maximize all-round performance of the circuit. This work is the first time that stacked nanosheet devices show advantages in electrical properties over the prevailing FinFET architecture. "SUNY Poly's partnership with IBM and Empire State Development is a ideal example of how Industry, Government and Academia can successfully collaborate and have a broad and positive impact on society". The development could lead to smaller, more powerful and more efficient devices - but with 10 nm chips only just hitting the market, and 7 nm due for commercial release in 2019, these 5 nm chips are probably still about four years away.

Chip-makers are looking to EUV lithography to stave off the death of Moore's Law.

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